The present invention relates to a semiconductor integrated circuit including a tristate output circuit such as a tristate gate, and moreover to diagnosis technique for such circuit, namely to a technology which is effective, for example, when applied to a gate array type semiconductor integrated circuits and ASIC (Application Specific Integrated Circuit) type microcomputer.
As a diagnosis technology for a semiconductor integrated circuit such as a microcomputer which is further increasing the scale of logic circuits, a scan bus system has been proposed. In this case, a test data input/output mode are provided for a semiconductor integrated circuit, in addition to the ordinary operation mode in order to enable effective diagnosis of many logic gates through external terminals and thereby a structure for easily inputting and outputting test data to internal registers is previously provided for the semiconductor integrated circuit. For instance, the scan bus is structured by adding the function as the shift register to each flip-flop within the semiconductor integrated circuit or the scan bus which inputs or outputs data to or from the predetermined group of the flip-flops by assigning the addresses to the flip-flops. In such scan bus structures, the test of complicated sequential circuits is concluded to the test for the combined circuit. Here, a fault in which the predetermined node is fixed to logic 0 or logic 1 is assumed, and a test pattern which enables detection of assumed faults of all nodes with the predetermined fault detecting rate is given to the semiconductor integrated circuit and a fault may be found by comparing the output pattern at this time with an expected value pattern.
As an example, the scan bus system has been described in the "NIKKEI ELECTRONICS" (P.308 to P.311, No. 400, issued on Jul. 28, 1986, NIKKEI McGraw-Hill).